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| 1 100 mhz to 32 00 mhz rx mixer with integrated fractional - n pll and vco data sheet ADRF6603 rev. b document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2010C 2013 analog devices, inc. all rights reserved. technical support www.analog.com features rx m ixer with integrated f ractional - n pll rf input f requency range : 11 00 mhz to 3 2 00 mhz internal lo frequency r ange: 2100 mhz to 260 0 mhz input p1db: 14 . 8 db m input ip3: 28.5 db m i i p3 o ptimization via e xternal p in ssb n oise f igure ip3set pin open : 1 4.3 db ip3se t pin at 3.3 v: 1 5 .6 db voltage c onversion g ain: 6 .7 db matched 200 ? if o utput i mpedance if 3 db b andwidth: 500 mhz programmable via 3 - wire spi i nterface 40- lead , 6 mm 6 mm lfcsp applications cellular b ase s tations general description the ADRF6603 is a high dynamic range active mixer with integrated phase - locked loop (pll) and voltage controlled oscillator (vco). the pll/synthesizer uses a fractional - n pll to generate a f lo input to the mixer. the reference input can be divided or multiplied and then appli ed to the pll phase frequency detector (pfd). the pll can support input reference frequencies from 12 mhz to 160 mhz. the pfd output controls a charge pump whose output drives an off - chip loop filter. the loop filter output is then applied to an integra ted vco. the vco output at 2 f lo is applied to a n lo divider , as well as to a programmable pll divider. the programmable pll divider is controlled by a sigma - delta ( - ) modulator (sdm). the modulus of the sdm can be programmed from 1 to 2047. the active mixer converts the single - ended 50 rf input to a 200 ? differential if output. the if output can operate up to 500 mhz. the adrf 6603 is fabricated using an advanced silicon - germanium bicmo s process. it is available in a 40 - lead, rohs - compliant , 6 mm 6 mm lfcsp with an exposed paddle . performance is specified over the ?40c to +85c temperature range. table 1. part no. internal lo range 3 db rf in balun range 1 db rf in balun range adrf6601 750 mhz 300 mhz 450 mhz 1160 mhz 2500 mhz 1600 mhz adrf6602 1550 mhz 1000 mhz 1350 mhz 2150 mhz 3100 mhz 2750 mhz ADRF6603 2100 mhz 1100 mhz 1450 mhz 2600 mhz 3200 mhz 2850 mhz adrf6604 2500 mhz 1200 mhz 1600 mhz 2900 mh z 3600 mhz 3200 mhz functional block dia gram mux r set cp vtune lodrv_en lon lop ip3set vcc1 2:1 mux vco core rf in temp sensor declvco decl2p5 decl3p3 ifp buffer buffer ifn vcc2 vcc_lo vcc_mix vcc_v2i vcc_lo nc ? + charge pump 250a, 500a (default), 750a, 1000a prescaler 2 le clk spi interface data muxout nc 3.3v ldo 2.5v ldo vco ldo div by 2, 1 pll_en ref_in gnd ADRF6603 internal lo range 2100mhz to 2600mhz 34 19 18 39 3 5 4 8 6 14 13 12 16 38 37 36 7 11 15 20 21 23 24 25 28 30 31 35 32 33 2 9 40 26 29 27 17 10 1 22 phase frequency detector third-order fractional interpolator fraction reg modulus integer reg n counter 21 to 123 2 2 4 08547-001 figure 1 .
ADRF6603 data sheet rev. b | page 2 of 32 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 rf specifications .......................................................................... 3 synthesizer/pll specifica tions ................................................... 4 logic input and power specifications ....................................... 4 timing characteristics ................................................................ 5 absolute maximum ratings ............................................................ 6 esd caution .................................................................................. 6 pin configuration and function descriptions ............................. 7 typical performance characteristics ............................................. 9 rf frequency sweep .................................................................... 9 if frequency sweep ................................................................... 10 spurious performance ................................................................ 15 register structure ........................................................................... 16 register 0 integer divide control (default: 0x0001c0) ..... 16 register 1 modulus divide control (default: 0x003001) .. 16 register 2 fractional divide control (default: 0x001802) .................................................................... 17 register 3 - modulator dither control (default: 0x10000b) ................................................................... 17 register 4 pll charge pump, pfd, and reference path control (default: 0x0aa7e4) ................................................... 18 register 5 pll enable and lo path control (default: 0x0000e5) ................................................................... 19 register 6 vco control and vco enable (default: 0x1e2106) ................................................................... 19 register 7 mixer bias enable and external vco enable (default: 0x000007) .................................................................... 19 theory of operation ...................................................................... 20 programming the ADRF6603 ................................................... 20 initialization sequence .............................................................. 20 lo sel ection logic ..................................................................... 21 applications information .............................................................. 22 basic connections for operation ............................................. 22 ac test fixture ............................................................................... 23 evaluation board ............................................................................ 24 evaluation board control software ......................................... 24 schematic and artwork ............................................................. 26 evaluation board configuration options ............................... 28 outline dimensions ....................................................................... 29 ordering guide .......................................................................... 29 revision history 10/13 rev. a to rev. b changed 2100 mhz to 2600 mhz to 1100 mhz to 3200 mhz in product title ............................................................ 1 updated outline dimensions ....................................................... 29 11 /10 rev. 0 to rev. a changes to features and general description ............................. 1 changes to table 1 ............................................................................ 1 changes to table 2 ............................................................................ 3 changes to table 3 and tabl e 4 ....................................................... 4 changes to table 6 ............................................................................ 6 change to table 7, pin 36 description .......................................... 8 changes to typical performance characteristics section ........... 9 added spurious performance section ......................................... 15 cha nges to programming the ADRF6603 section .................... 20 changes to figure 46 ...................................................................... 22 added ac test fixture section and figure 47; renumbered sequentially ............................................................. 2 3 changes to evaluation board control software section ; changes to figure 4 8 ...................................................................... 24 changes to figure 49 ...................................................................... 25 changes to figure 50 ...................................................................... 26 1/10 revision 0: initial version data sheet ADRF6603 rev. b | page 3 of 32 specifications rf specifications v s = 5 v; ambient temperature (t a ) = 25c; f ref = 153.6 mhz; f pfd = 38.4 mhz; high - side lo injection; f if = 140 mhz; iip3 optimized usi ng c dac ( 0x1 ) and ip3set ( 3.3 v ) , unless otherwise noted. table 2. parameter test conditions /comments min typ max unit internal lo frequency range 2100 2600 mhz rf input frequency range 3 db rf input range 1100 3200 mhz rf i nput at 214 0 mhz input return l oss relative to 50 ? (can be improved with external match) <( ? 20) db input p1db 14.9 dbm second - order intercept (iip2) ? 5 dbm each tone (10 mhz spacing between tones) 55.3 dbm third - order intercept (iip3) ? 5 dbm each tone (10 mhz spacing between tones) 29.3 dbm single - side band noise figure ip3set = 3.3 v 15.6 db ip3set = open 14.4 db lo -to -i f leakage at 1 lo f requency, 50 ? t ermination at the rf p ort ? 43 dbm rf input at 240 0 mhz input return loss relative to 50 ? (can be improved with external m atch) ? 16 db input p1db 14.9 dbm second - order intercept (iip2) ? 5 dbm each tone (10 mhz spacing between tones) 55.1 dbm third - order intercept (iip3) ? 5 dbm each tone (10 mhz spacing between tones) 28.6 dbm single - side band noise figure ip3set = 3.3 v 15.8 db ip3set = open 14. 2 db lo -to - if leakage at 1 lo frequency, 50 ? termination at the rf port ? 43 dbm rf input at 265 0 mhz input return loss relative to 50 ? (can be improved with external match) ? 11 db input p1db 14.7 db m second - order intercept (iip2) ? 5 dbm each tone (10 mhz spacing between tones) 52.1 dbm third - order intercept (iip3) ? 5 dbm each tone (10 mhz spacing between tones) 28.1 dbm single - side band noise figure ip3set = 3.3 v 15.8 db ip3set = open 14.5 db lo -to - if leakage at 1 lo frequency, 50 ? termination at the rf port ? 44 dbm if output voltage conversion gain differential 200 ? load 6. 7 db if bandwidth small signal 3 db bandwidth 500 mhz output common - mode voltage external pull -u p balun or inductors required 5 v gain flatness over frequency range, any 5 mhz/50 mhz 0.2/ 1.0 db gain variation over full temperature range 1.2 db output swing differential 200 ? load 2 v p -p differential output return loss measured through 4: 1 balun ? 1 5 db lo input/output (lop, lon) externally applied 1 lo input, internal pll disabled frequency range 250 6000 mhz output level (lo as output) 1 lo into a 50 ? load, lo output buffer enabled ? 7 dbm input level (lo as input) ? 6 0 + 6 dbm input impedance 50 ? ADRF6603 data sheet rev. b | page 4 of 32 synthesizer/pll spec ifications v s = 5 v; ambient temperature (t a ) = 25c; f ref = 153.6 mhz; f ref power = 4 dbm ; f pfd = 38.4 mhz; high - side lo injection; f if = 140 mhz; iip3 optimized using c dac (0x1 ) and ip3set (3.3 v), unless otherwise noted. table 3. parameter test conditions /comments min typ max unit synthesizer specifications synthesizer s pecifications r eferenced to 1 lo frequency range internally g enerated lo 2100 2600 mhz figure of m erit 1 p ref _in = 0 dbm ? 222 dbc/hz /hz reference spurs f pfd = 38.4 mhz f pfd /4 ? 107 dbc f pfd ? 82 dbc > f pfd ? 85 dbc phase noise f lo = 210 0 mhz to 260 0 mhz, f pfd = 38.4 mhz 1 khz to 10 khz offset ? 88 dbc/hz 100 khz offset ? 99.5 dbc/hz 500 khz offset ? 120 dbc/hz 1 mhz offset ? 128 dbc/hz 5 mhz offset ? 142 dbc/hz 10 mhz offset ? 148 dbc/hz 20 mhz offset ? 150 dbc/hz integrated phase noise 1 k hz to 4 0 mhz integration bandwidth 0.42 rms pfd frequency 20 40 mhz reference characterist ics ref_in, muxout pins ref_in input frequency 12 160 mhz ref_in input capacitance 4 pf muxout output level v ol (lock detect output selected) 0.25 v v oh (lock detect output selected) 2.7 v muxout duty cycle 50 % charge pump pum p current programmable to 250 a, 500 a, 750 a, 1 m a 500 a output compliance range 1 2.8 v 1 the figure of merit (fom) is computed as phase noise (dbc/hz) C 10log10(f p f d ) C 20log10(f lo /f p f d ). the fom was measured across the full lo range, with f ref = 80 mhz, and f ref power = 10 dbm (500 v/s slew rate) with a 40 mhz f pfd . the fom was computed at 50 khz offset. logic input and powe r specifications v s = 5 v; ambient temperature (t a ) = 25c; f ref = 153.6 mhz; f pfd = 38.4 mhz; high - side lo injection; f if = 140 mhz; iip3 optimized using c dac (0x 1 ) and ip3set (3.3 v), unless otherwise noted. table 4. parameter test conditions /comments min typ max unit logic inputs clk, data, le input high voltage , v inh 1.4 3.3 v input low voltage , v inl 0 0.7 v input current , i inh /i inl 0.1 a input capacitance , c in 5 pf power supplies vcc 1, vcc2, vcc_lo , vcc_mix, and vcc_v2i pins voltage range 4.75 5 5.25 v supply current pll only 97 ma external lo mode (internal pll disabled, lo o u tput buffer off , ip3set pin = 3.3 v) 164 ma internal lo mode (internal pll enabled , ip3set pin = 3.3 v , lo output buffer on ) 2 74 ma internal lo mode (internal pll enabled, ip3set pin = 3.3 v , lo output buffer off ) 261 ma power - down mode 30 ma data sheet ADRF6603 rev. b | page 5 of 32 timing characteristi cs v cc2 = 5 v 5 %. table 5. parameter limit unit description t 1 20 ns min le setup time t 2 10 ns min data -to - cl k setup time t 3 10 ns min data -to - clk hold time t 4 25 ns min clk h igh duration t 5 25 ns min c lk l ow d uration t 6 10 ns min clk - to - le s etup t ime t 7 20 ns min le p ulse w idth timing diagram c l k da t a l e d b 23 (ms b ) d b 2 2 d b 2 d b 1 ( c o n t r o l b i t c 2 ) ( c o n t r o l b i t c 3) d b 0 ( l s b ) ( c o n t r o l b i t c 1 ) t 1 t 2 t 3 t 7 t 6 t 4 t 5 08547-002 figure 2 . timing diagram ADRF6603 data sheet rev. b | page 6 of 32 absolute maximum rat ings table 6. parameter rating supply voltage , vcc 1 , vcc 2, v cc_lo, vcc_mix, vcc_v2i ? 0.5 v to +5.5 v digital i/o , clk, data, le , lodrv_en, pll_en ? 0.3 v to + 3.6 v vtune 0 v to 3.3 v ifp, ifn ? 0.3 v to vcc _v2i + 0.3 v rf in 16 dbm lop, lon , ref_in 13 dbm ja (exposed paddle soldered down) 35c/w maximum junction temperature 150c op erating temperature range ? 40c to +85c storage temperature range ? 65c to +150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution data sheet ADRF6603 rev. b | page 7 of 32 pin configuration and function descrip tions pin 1 indicator notes 1. nc = no connect. 2. the exposed paddle should be soldered to a low impedance ground plane. 1 vcc1 2 decl3p3 3 cp 4 gnd 5 r set 6 ref_ in 7 gnd 8 muxout 9 decl2p5 10 vcc2 23 gnd 24 gnd 25 gnd 26 rf in 27 vcc_v2i 28 gnd 29 ip3set 30 gnd 22 vcc_mix 21 gnd 11 gnd 12 data 13 clk 15 gnd 17 vcc_lo 16 pll_en 18 ifp 19 ifn 20 gnd 14 le 33 nc 34 vcc_lo 35 gnd 36 lodrv_en 37 lon 38 lop 39 vtune 40 declvco 32 nc 31 gnd top view (not to scale) ADRF6603 08547-003 figure 3 . pin configuration table 7 . pin function descriptions pin no. mnemonic description 1 vcc 1 power supply for the 3.3 v ldo . power supply voltage range is 4.75 v to 5.25 v. each power supply pin should be decoupled with a 100 p f capacitor and a 0.1 f capacitor located close to the pin. 2 decl3p3 decoupling node for 3.3 v ldo . connect a 0.1 f capacitor between this pin and ground. 3 cp charge p ump output pin. connect to vtune through the loop filter . 4 , 7 , 11, 15, 20 , 21, 23, 24, 25, 28, 30, 31, 35 gnd ground . connect these pins to a low impedance ground plane. 5 r set charge pump current . the nominal charge pump current can be set to 250 a, 500 a , 750 a, or 1 ma usi ng bit db1 1 and bit db1 0 in register 4 and by setting bit db18 in register 4 to 0 (i nternal reference c urrent). in this mode, no external r set is required. if bit db18 is set to 1, the four nominal charge pump currents (i nominal ) can be externally adjusted according to the following equation: 37.8 4 . 217 ? ? ? ? ? ? ? ? ? = nominal cp set i i r 6 ref _in reference input . nominal input level is 1 v p - p. input range is 12 mhz to 160 mhz. this pin is internally dc - biased and should be ac - coupled. 8 muxout multiplexer output . this output can be programmed to provide the reference o utput signal or the l ock d etect signal. the output is selected by programming the appropriate register. 9 decl2p5 decoupling node for 2.5 v ldo . connect a 0.1 f capacitor between this pin and ground. 10 vcc2 power supply for the 2.5 v ldo . power supply voltage range is 4.75 v to 5.25 v. each power supply pin should be decoupled with a 100 pf capacitor and a 0.1 f capacitor located close to the pin. 12 data serial data input . the serial data input is loaded m sb first ; the three lsbs are the control bits. 13 clk serial clock input . th e serial clock input is used to clock in the serial data to the registers. the data is latched into the 24 - bit shift register on the clk rising edge. maximum clock frequency is 20 mhz. 14 le load enable . when the le input pin goes high, the data stored in the shift registers is loaded into one of the eight registers. t he relevant latch is selected by the three control bits of the 24 - bit word. 16 pll_en pll enable . switch between i nternal pll and external lo i nput. when this pin is logic high , the mixer lo is automatically switched to the internal pll and the internal pll is powered up. when this pin is logic low , the internal pll is powered down and the external lo input is routed to the mixer lo inputs. the spi can also be used to switch modes. ADRF6603 data sheet rev. b | page 8 of 32 pin no. mnemonic description 17, 34 vcc_lo power supply. power supply voltage range is 4.75 v to 5.25 v. each power supply pin should be decoupled with a 100 pf capacitor and a 0.1 f capacitor located close to the pi n. 18, 19 ifp , ifn mixer if outputs . these outputs s hould be pulled to vcc with rf c hokes . 22 vcc _mix power supply. power supply voltage range is 4.75 v to 5.25 v. each power supply pin should be decoupled with a 100 pf capacitor and a 0.1 f capacitor l ocated close to the pin. 26 r f in rf input (single - ended, 50 ? ). 27 vcc_v2i power supply. power supply voltage range is 4.75 v to 5.25 v. each power supply pin should be decoupled with a 100 pf capacitor and a 0.1 f capacitor located close to the pin. 29 ip3set connec t a resistor from t his pin to a 5 v supply to adjust i i p3. no rm ally leave open . 32, 33 nc no connection . 36 lodrv_en lo driver enable . together with pin 16 (pll_en), this digital input pin determines whether the lop and lon pin s operate as inputs or outputs . lop and lon be come inputs if the pll_en pin is low or if the pll_en pin is set high with the plen bit (db6 in register 5 ) set to 0 . lop and lon become outputs if either the lodrv_en pin or the ldrv bit ( db3 in register 5 ) is set to 1 while the pll_en pin is set high. ex ternal lo drive frequency must be 1 lo . this pin has an internal 100 k? pull down resistor. 37, 38 lon, lop local oscillator input/output . the internally generated 1 lo is available on these pins. when internal lo generation is disabled, an external 1 lo can be applied to these pins. 39 vtune vco control voltage input . this pin is driven by the output of the loop filter. nominal input voltage range on this pin is 1.5 v to 2.5 v . 40 declvco decoupling node for vco ldo . connect a 100 pf capacitor and a 10 f capacitor between this pin and ground. ep ad exposed paddle. the exposed paddle should be soldered to a low impedance ground plane. data sheet ADRF6603 rev. b | page 9 of 32 typical performance characteristics rf frequency sweep cdac = 0x 1 , internally generated high - side lo, rf in = ? 5 dbm, f if = 140 mhz , unless otherwise noted. 5 ?5 ?4 ?3 ?2 ?1 0 1 2 3 4 1960 2010 2060 2110 2160 2210 2260 2310 2360 2410 2460 gain (db) rf frequency (mhz) ip3set = open ip3set = 3.3v t a = ?40c t a = +25c t a = +85c 08547-104 figure 4 . gain vs. rf frequency 90 80 70 60 50 40 30 1960 2010 2060 2110 2160 2210 2260 2310 2360 2410 2460 input ip2 (dbm) rf frequency (mhz) ip3set = open ip3set = 3.3v t a = ?40c t a = +25c t a = +85c 08547-105 figure 5 . i nput ip2 vs. rf frequency 20 18 16 14 12 10 8 6 4 2 0 1960 2010 2060 2110 2160 2210 2260 2310 2360 2410 2460 noise figure (db) rf frequency (mhz) ip3set = open ip3set = 3.3v t a = ?40c t a = +25c t a = +85c 08547-106 figure 6 . noise figure vs. rf frequenc y 40 35 30 25 20 15 1960 2010 2060 2110 2160 2210 2260 2310 2360 2410 2460 input ip3 (dbm) rf frequency (mhz) ip3set = open ip3set = 3.3v t a = ?40c t a = +25c t a = +85c 08547-107 figure 7 . i nput ip3 vs. rf frequency 20 19 18 17 16 15 14 13 12 11 10 1960 2010 2060 2110 2160 2210 2260 2310 2360 2410 2460 input p1db (dbm) rf frequency (mhz) ip3set = open ip3set = 3.3v t a = ?40c t a = +25c t a = +85c 08547-108 figure 8 . i nput p1db vs. rf frequency ADRF6603 data sheet rev. b | page 10 of 32 i f frequency sweep cdac = 0x 1 , internally generated swept low - side lo , f r f = 1960 mhz , r f in = ?5 dbm, unless otherwise noted . 5 ?5 ?4 ?3 ?2 ?1 0 1 2 3 4 25 50 75 100 125 150 175 200 225 250 275 300 325 350 375 400 gain (db) ip3set = open ip3set = 3.3v t a = ?40c t a = +25c t a = +85c if frequency (mhz) 08547-109 fig ure 9 . gain vs. if frequency 90 80 70 60 50 40 30 25 50 75 100 125 150 175 200 225 250 275 300 325 350 375 400 input ip2 (dbm) ip3set = open ip3set = 3.3v t a = ?40c t a = +25c t a = +85c if frequency (mhz) 08547-110 figure 10 . i nput ip2 vs. if frequency, rf in = ?5 dbm 20 18 16 14 12 10 8 6 4 2 0 25 400 375 350 325 300 275 250 225 200 175 150 125 75 50 100 noise figure (db) if frequency (mhz) t a = ?40c t a = +25c t a = +85c ip3set = open ip3set = 3.3v 08547-111 figure 11 . noise figure vs. if frequency 45 40 35 30 25 20 15 10 5 25 400 375 350 325 300 275 250 225 200 175 150 125 75 50 100 input ip3 (dbm) if frequency (mhz) ip3set = open ip3set = 3.3v t a = ?40c t a = +25c t a = +85c 08547-112 figure 12 . i nput ip3 vs. if frequency, rf in = ?5 dbm 25 400 375 350 325 300 275 250 225 200 175 150 125 75 50 100 20 18 16 14 12 10 8 6 4 2 0 input p1db (dbm) if frequency (mhz) ip3set = open ip3set = 3.3v t a = ?40c t a = +25c t a = +85c 08547-113 figure 13 . i nput p1db vs. if frequency data sheet ADRF6603 rev. b | page 11 of 32 0 ?60 ?55 ?50 ?45 ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 2100 2150 2200 2250 2300 2350 2400 2450 2500 2550 2600 lo-to-if feedthrough (dbm) lo frequency (mhz) ip3set = open ip3set = 3.3v t a = ?40c t a = +25c t a = +85c 08547-114 figure 14 . lo - to - if feedthrough vs. lo frequency, lo output turned off, cdac = 0x0 ?20 ?90 ?85 ?80 ?75 ?70 ?65 ?55 ?60 ?50 ?45 ?40 ?35 ?30 ?25 2100 2600 2500 2400 2300 2200 lo-to-rf leakage (dbm) lo frequency (mhz) ip3set = open ip3set = 3.3v t a = ?40c t a = +25c t a = +85c 08547-115 figure 15 . lo - to - rf leakage vs. lo frequency, lo output turned off 0 ?45 ?35 ?40 ?30 ?25 ?20 ?15 ?10 ?5 1900 2800 2700 2600 2500 2400 2300 2200 2100 2000 return loss (db) rf frequency (mhz) 08547-116 figure 16 . rf input return loss vs. rf frequency 0 ?20 ?18 ?16 ?14 ?12 ?10 ?8 ?6 ?4 ?2 1900 2800 2700 2600 2500 2400 2300 2200 2100 2000 return loss (db) lo frequency (mhz) 08547-117 figure 17 . lo input return loss vs. lo frequency (including tc1 - 1 - 13 balun) 350 0 50 100 150 200 250 300 3.5 0 0.5 1.0 1.5 2.0 2.5 3.0 50 500 450 400 350 300 250 200 150 100 resistance (?) capacitance (pf) if frequency (mhz) capacitance resistance 08547-118 figure 18 . if differential output impedance (r parallel c equivalent) 35 10 15 20 25 30 ?60 ?50 ?40 ?30 ?20 ?10 0 noise figure (db) cw blocker level (dbm) ip3set = open ip3set = 3.3v 08547-119 figure 1 9 . ssb noise figure vs. 5 mhz offset blocker level, lo frequency = 2105 mhz, rf frequency = 1965 mhz ADRF6603 data sheet rev. b | page 12 of 32 0 ?60 ?55 ?50 ?45 ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 1900 2800 2700 2600 2500 2400 2300 2200 2100 2000 rf-to-if isolation (db) lo frequency (mhz) ip3set = open ip3set = 3.3v t a = ?40c t a = +25c t a = +85c 08547-120 figure 20 . rf - to - if isolation vs. rf frequency, high - side lo, if = 140 mhz, lo output turned off ?2 ?12 ?3 ?4 ?5 ?6 ?7 ?8 ?9 ?11 ?10 2100 2150 2200 2250 2300 2350 2400 2450 2500 2550 2600 lo output amplitude (dbm) lo frequency (mhz) ip3set = open ip3set = 3.3v t a = ?40c t a = +25c t a = +85c 08547-121 figure 21 . lo output amplitude vs. lo frequency 20 15 10 5 0 ?5 ?10 ?15 ?20 0 50 100 150 200 250 frequency deviation from 2140mhz (mhz) time (s) 08547-122 figure 22 . frequency deviation from 2140 mhz vs time (d emonstrates lo frequency settling t ime from 2150 mhz to 2140 mhz) 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 2100 2200 2300 2400 2500 2600 vtune voltage (v) lo frequency (mhz) t a = ?40c t a = +25c t a = +85c 08547-123 figure 23 . v tune vs. lo frequency 350 100 150 200 250 300 2100 2600 2550 2500 2450 2400 2350 2300 2250 2200 2150 supply current (ma) lo frequency (mhz) ip3set = open ip3set = 3.3v t a = ?40c t a = +25c t a = +85c 08547-124 figure 24 . supply current vs. lo frequency 2.0 2.1 2.2 2.3 2.4 2.5 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 ?55 ?35 ?15 5 25 45 65 85 105 vptat voltage (v) temperature (c) ip3set = open ip3set = 3.3v 08547-125 figure 25 . vptat voltage v s. temperature (ip3s et = optimized , o pen) data sheet ADRF6603 rev. b | page 13 of 32 complementary cumulative distribution function (ccdf), f rf = 2140 mhz, f if = 140 mhz. 100 0 10 20 30 40 50 60 70 80 90 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 distribution percentage (%) gain (db) ip3set = open ip3set = 3.3v t a = ?40c t a = +25c t a = +85c 08547-126 figure 26 . gain 100 0 10 20 30 40 50 60 70 80 90 40 45 50 55 60 65 70 distribution percentage (%) input ip2 (dbm) ip3set = open ip3set = 3.3v t a = ?40c t a = +25c t a = +85c 08547-127 figure 27 . i nput ip2 100 0 10 20 30 40 50 60 70 80 90 11 12 13 14 15 16 17 18 distribution percentage (%) noise figure (db) ip3set = open t a = ?40c t a = +25c t a = +85c 08547-128 figure 28 . noise figure 100 0 10 20 30 40 50 60 70 80 90 20 22 24 26 28 30 32 34 36 distribution percentage (%) input ip3 (dbm) ip3set = open ip3set = 3.3v t a = ?40c t a = +25c t a = +85c 08547-129 figure 29 . i nput ip3 100 0 10 20 30 40 50 60 70 80 90 9 10 11 12 13 14 15 16 18 17 distribution percentage (%) input p1db (dbm) ip3set = open ip3set = 3.3v t a = ?40c t a = +25c t a = +85c 08547-130 figure 30 . i nput p1db 100 0 10 20 30 40 50 60 70 80 90 ?55 ?53 ?51 ?49 ?47 ?45 ?43 ?41 ?39 ?37 ?35 distribution percentage (%) lo feedthrough (dbm) ip3set = open ip3set = 3.3v t a = ?40c t a = +25c t a = +85c 08547-131 figure 31 . lo feedthrough to if, lo output turned off ADRF6603 data sheet rev. b | page 14 of 32 measured at if o utput, cdac = 0x 1 , ip3set = open , internally generated high - side lo, f ref = 153.6 mhz, f pfd = 38.4 mhz , rf in = ?5 dbm, f if = 140 mhz, unless otherwise noted. phase noise measurements made at lo output, unless otherwise noted. ?80 ?160 ?150 ?140 ?130 ?120 ?110 ?100 ?90 1k 10k 100k 1m 10m 100m phase noise (dbc/hz) offset frequency (hz) lo frequency = 2595.2mhz lo frequency = 2115.2mhz t a = ?40c t a = +25c t a = +85c 08547-132 figure 32 . phase noise vs . offset frequency ?75 ?110 ?105 ?100 ?95 ?90 ?85 ?80 2100 2150 2200 2250 2300 2350 2400 2450 2500 2550 2600 spurrs level (dbc) lo frequency (mhz) 2 pfd frequency 4 pfd frequency t a = ?40c t a = +25c t a = +85c 08547-133 figure 33 . pll reference spurs vs. lo frequency ( 2 pfd and 4 pfd ) ?75 ?110 ?105 ?100 ?95 ?90 ?85 ?80 2100 2150 2200 2250 2300 2350 2400 2450 2500 2550 2600 spurrs level (dbc) lo frequency (mhz) 3 pfd frequency 1 pfd frequency t a = ?40c t a = +25c t a = +85c 0.25 pfd frequency 08547-134 figure 34. pll reference spurs vs. lo frequency ( 0.25 pfd, 1 pfd, and 3 pfd ) 1.0 0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.1 0.2 2100 2600 2550 2500 2450 2400 2350 2300 2250 2200 2150 integrated phase noise (rms) lo frequency (mhz) t a = ?40c t a = +25c t a = +85c 08547-135 figure 35 . integrated phase noise vs. lo frequency ?80 ?90 ?100 ?110 ?120 ?130 ?140 ?150 ?160 phase noise (dbc/hz) lo frequency (mhz) offset = 5mhz offset = 100khz t a = ?40c t a = +25c t a = +85c 2100 2600 2550 2500 2450 2400 2350 2300 2250 2200 2150 offset = 1khz 08547-136 figure 36 . phase noise vs. lo frequency (1 khz, 100 khz, and 5 mhz steps) ?80 ?90 ?100 ?110 ?120 ?130 ?140 ?150 ?160 phase noise (dbc/hz) lo frequency (mhz) offset = 1mhz t a = ?40c t a = +25c t a = +85c 2100 2600 2550 2500 2450 2400 2350 2300 2250 2200 2150 offset = 10khz 08547-137 figure 37 . phase noise vs. lo frequency (10 khz, 1 mhz steps) data sheet ADRF6603 rev. b | page 15 of 32 spurious p erformance (n f rf ) ? (m f lo ) spur measurements w ere m ade using the standard evaluation board (see the evaluation board section ) . mixer spurious products were measured in db relative to the carrier (dbc) from th e if output power level. all spurious components greater than ? 125 dbc are shown . lo = 2280 mhz, rf = 2140 mhz (horizontal axis is m, vertical axis is n), and rf in power = 0 dbm. m n 0 1 2 3 4 0 ? 114.35 ? 45.19 ? 36.94 1 ? 20.79 0.0 ? 67.43 ? 52.11 2 ? 58.20 ? 61.95 ? 78.15 ? 85.93 ? 93.10 3 ? 71.79 ? 91.89 ? 67.46 ? 105.88 4 ? 107.79 ? 110.27 ? 107.87 5 ? 107.88 ? 112.41 6 ? 107.71 7 ? 108.62 lo = 2540 mhz, rf = 2400 mhz (horizontal axis is m, vertical axis is n), and rf in power = 0 dbm. m n 0 1 2 3 4 0 ? 113.65 ? 47.04 ? 36.36 1 ? 18.91 0.0 ? 65.01 ? 56.24 2 ? 59.08 ? 60.49 ? 69.27 ? 89.85 ? 94.25 3 ? 77.54 ? 89.56 ? 68.39 ? 109.30 4 ? 108.79 ? 110.65 ? 111.94 5 ? 108.85 ? 111.54 6 ? 108.89 7 lo = 2650 mhz, rf = 2510 m hz (horizontal axis is m, vertical axis is n), and rf in power = 0 dbm. m n 0 1 2 3 4 0 ? 111.38 ? 46.57 ? 36.03 1 ? 17.70 0.0 ? 65.70 ? 54.37 2 ? 58.49 ? 75.49 ? 72.27 ? 71.05 ? 95.32 3 ? 81.35 ? 89.18 ? 68.23 ? 103.38 4 ? 106.13 ? 106.74 ? 112.72 5 ? 107.26 ? 105.45 6 ? 110.74 7 ADRF6603 data sheet rev. b | page 16 of 32 r egister s tructure this section provides the register m aps for the adrf 6603 . the three lsbs determine the register that is programmed . register 0 i nteger divide contro l ( default : 0 x 0001c0) divide mode db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 0 0 0 0 0 0 0 0 0 dm id6 id5 id4 id3 id2 id1 id0 c3(0) c2(0) c1(0) dm 0 1 id6 id5 id4 id3 id2 id1 id0 0 0 1 0 1 0 1 0 0 1 0 1 1 0 0 0 1 0 1 1 1 0 0 1 1 0 0 0 ... ... ... ... ... ... ... ... ... ... ... ... ... ... 0 1 1 1 0 0 0 ... ... ... ... ... ... ... ... ... ... ... ... ... ... 1 1 1 0 1 1 1 1 1 1 1 0 0 0 1 1 1 1 0 0 1 1 1 1 1 0 1 0 1 1 1 1 0 1 1 ... ... 119 120 (integer mode only) integer divide ratio 21 (integer mode only) 22 (integer mode only) 23 (integer mode only) 24 ... ... 56 (default) integer integer divide ratio control bits divide mode fractional (default) 121 (integer mode only) 122 (integer mode only) 123 (integer mode only) reserved 08547-004 figure 38 . register 0 integer divide control register map register 1 m odulus divide control (defa ult: 0 x003001) modulus value db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 0 0 0 0 0 0 md10 md9 md8 md7 md6 md5 md4 md3 md2 md1 md0 c3(0) c2(0) c1(1) md10 md9 md8 md7 md6 md5 md4 md3 md2 md1 md0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... 1 1 0 0 0 0 0 0 0 0 0 ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... 1 1 1 1 1 1 1 1 1 1 1 modulus value ... ... 2047 control bits 1 1536 (default) 2 ... ... reserved 08547-005 figure 39 . register 1 modulus divide control register map data sheet ADRF6603 rev. b | page 17 of 32 r egister 2 f ractional d ivide c ontrol ( default : 0x001802) fd10 fd9 fd8 fd7 fd6 fd5 fd4 fd3 fd2 fd1 fd0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... 0 1 1 0 0 0 0 0 0 0 0 ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... fractional value must be less than modulus fractional value 0 1 ... ... 768 (default) ... ... data sheet ADRF6603 rev. b | page 19 of 32 register 5 pll enable and lo path control (def ault: 0 x 0000e5) 08547-009 reserved res pll en lo div1 lo ext lo drv db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 ldv2 db6 db5 db4 db3 db2 db1 db0 cd3 cd2 cd1 cd0 plen ldv1 lxl ldrv c3(1) c2(0) c1(1) ldrv 0 1 lxl 0 1 ldv1 0 1 divide by 1 divide by 2 (default) lo output driver enable driver off (default) driver on plen 0 1 disable enable (default) pll enable external lo drive enable (pin 37, pin 38) internal lo output (default) external lo input divide-by-2 in lo chain enable cap dac control bits cd3 cd2 cd1 cd0 0 0 0 0 ... ... ... ... min ... capacitor dac control for iip3 optimization 1 1 1 1 max 0 0 0 0 0 0 0 0 0 0 0 0 figure 43 . register 5 pll enable and lo path control register map register 6 vco control and vco enable ( default : 0x1e2106) charge pump enable 3.3v ldo enable vco enable vco switch vco bw sw ctrl vbsrc 0 1 vco en vco ldo enable vco amplitude reserved vco band select from spi vbs[5:0] vco band select from spi 0x00 default 0x20 charge pump enable 0x01 ?. 0x00 0 ?. ?. 0x18 24 (default) ?. ?. 0x2b 43 ?. ?. 0x3f 63 (recommended) 0x3f vco bw cal and sw source control band cal (default) vco sw 0 1 vco switch control from spi regular (default) band cal spi vco enable disable enable (default) db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 control bits db23 cpen l3en vco en vco sw vc5 vc4 vc3 vc2 vc1 vc0 vbsrc vbs5 vbs4 vbs3 vbs2 vbs1 vbs0 c3(1) c2(1) c1(0) lven vc[5:0] vco amplitude 0 1 lven vco ldo enable disable enable (default) 0 1 l3en 3.3v ldo enable disable enable (default) 0 1 cpen disable enable (default) 0 1 0 0 0 08547-010 figure 44 . register 6 vco control and vco enable register map r egister 7 mixer bias enable and exte rnal vco enable ( default : 0x 000007) db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 0 xvco xvco res mbe 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 c3(1) c2(1) c1(1) mixer b_en reserved control bits mbe 0 1 xvco 0 1 internal vco (default) external vco mixer bias enable enable (default) disable external vco 08547-011 figure 45 . register 7 mixer bia s enable and external vco enable register map ADRF6603 data sheet rev. b | page 20 of 32 theory of operat i on the adrf 6603 integrates a h igh performance down converting mixer with a state - of - the - art fractional - n pll. the pll also inte grates a low noise vco. the spi port allows the user to control the fractional - n pll functions and the m ixe r optimization functions , as well as allowing for an externally applied lo or vco. the mixer core within the adrf 6603 is the next generation of an industry - leading family of m ixe rs from analog devices , inc . the rf input i s converted to a current and then mixed down to i f using high performance npn transistors. the mixer output currents ar e transformed to a differential output . the high performance active mixer core results in an exceptional iip3 and i p1db, with a very low output noise floor for excellent dynamic range. over the specified frequency range , the adrf 6603 typically provide s if in put p1db of 1 4. 6 db m and iip3 of 27 db m. improved performance at specific frequencies can be achieved with the use of the internal capacitor dac (cdac) , which is programmable via the spi po rt, and by using a resi stor to a 5 v supply from the ip3set pin (p in 29). adjust ment of the capacitor dac allows increments in phase shift at internal nodes in the adrf 6603 , thus allowing can cellation of third - order distortion with no change in supply current. connecting a resistor to a 5 v supply from the ip3set pin increases the internal m ixe r core current, th ereby improving overall i i p2 and i ip3, as well as i p1db. using the ip3set pin for t his purpose increase s the overall supply current. the fractional divide function of the pll allows the frequency multipl ication value from ref _ in to lo o ut put to be a fractional value rather than be restricted to an integer value as in traditional plls. in operation, this multiplication value is int + (frac/mod) , where int is the integer value, frac is the fractional value , and mod is the modulus value, all programmable via the spi port. in other frac tional - n pll designs, fractional multiplication is achie ved by periodically changing the fractional value in a deterministic way. the disadvantage of this approach is often spurious components close to the fundamental signal. in the adrf 6603 , a - modulator is used to distribute the fractional value randomly, thus significantly reducing the spurious content due to the fr actional function. programming the adrf 6603 the adrf 6603 is programmed via a 3 - pin spi port. the timing requirements for the spi port are shown in figure 2 . e ight pro - grammable regist ers, each with 24 bits, contr ol the operation of the device. the register functions are listed in table 8 . table 8. adrf 6603 register functions regi ster function register 0 integer divide control for the pll register 1 modulus divide control for the pll register 2 fractional divide control for the pll register 3 - modulator dither control register 4 pll charge pump, pfd, reference path control register 5 pll enable and lo path control register 6 vco control and vco enable register 7 mixer bias enable and e xternal vco enable note that internal calibration for the pll must be run when the adrf 6603 is initialized at a given frequency. this calibration is run automatically whenever r egister 0, register 1, or register 2 is programmed. because the other registers affect pll performance, register 0, register 1, and register 2 should a lways be programmed last and in th is order: register 0, register 1, register 2 . to program the frequency of the adrf 6603, the user typically programs only r egister 0 , register 1, and register 2 . however, if registers other than these are programmed first, a short delay should be inserted before programming r egister 0. this delay e nsure s that the vco band calibration has sufficient time to complete before the final band calibration for r egiste r 0 is initiated. software is available on the adrf 6603 product page under the evaluation boards & development kits section that allows easy programming from a pc running windows xp or vista. i nitia l ization sequence to ensure proper power - up of the adrf 6603 , it is important to reset the pll circuitry after the vcc supply rail settles to 5 v 0.25 v. resetting the pll ensures that the internal bias cells are properly configured, even under poor supply start - up conditions. to ensure that the pll is reset after power - up, follow this procedure: 1. disable the pll by setting the plen bit to 0 (register 5, bit db6). 2. after a delay of >100 m s, set the plen bit to 1 (register 5, bit db6) . after this procedure is followed, the other registers should be programmed in this order: register 7, register 6, register 4, register 3, register 2, register 1. then, after a delay of >100 ms, register 0 sho uld be programmed. data sheet ADRF6603 rev. b | page 21 of 32 lo selection logic the down converting mixer in the adrf 6603 can be used without the internal pll by applying an external differential lo to pin 37 and pin 38 (lo n an d lop ). in addition, when using an lo generated by the internal pll, the lo signal can be accessed directly at these same pins. this function can be used for debugging purposes , or the internally generated lo can be used as the lo for a separate mixer. th e operation of the lo generation and whether lop and lon are input s or output s are determined by the logic levels applied at pin 16 (pll_en) and p in 36 (lodrv_en) , as well as b it db 3 (ldrv) and bit db 6 (plen) in r egister 5. the combination of externally ap plied logic and internal bits required for particular lo functions is given in table 9 . table 9 . lo selection logic pins 1 register 5 bits 1 outputs pin 16 (pll_en) pin 36 (lodrv_en) bit db6 (plen) bit db3 (ldrv) output buffer lo 0 x 0 x disabled external 0 x 1 x disabled external 1 x 0 x disabled external 1 0 1 0 disabled internal 1 x 1 1 enabled internal 1 1 1 x enabled internal 1 x = dont care. ADRF6603 data sheet rev. b | page 22 of 32 applications info rmation basic connections fo r operation figure 46 shows the schematic for the adrf 6603 evaluation board. the six power supply pins should be individ ually decoupled using 100 pf and 0.1 f capacitors located as close as possible to the device. in addition, the internal decoupling nodes (decl 3p3, decl2p5, and declvco ) should be decoupled with the capacitor values shown in figure 46. the rf input is i nternally ac - coupled and needs no external bias. the if outputs are open collector , and a bias inductor is required from these outputs to vcc. a peak - to - peak differential swing on rf i n of 1 v (0.353 v rms for a sine w ave input) results in an if output power of 4.7 dbm. the reference frequency for the pll should be from 12 mhz to 160 mhz and should be applied to the ref _ in pin , which should be ac - coupled and terminated with a 50 ? resistor as shown in figure 46 . the reference signal , or a divided - down version of the r eference signal , can be brought back off chip at the mu ltiplexer output pin (muxout). a lock detect signal and a voltage proportional to the ambient temperature ca n also be selected on the multiplexer output pin . the loop filter is connected between the cp and vtune pins. when connected in this way , the internal vco is operational. for information about th e loop filter compon ents , see the evaluation board configuration options section. operation with an external vco is also possible. in this case, the loop filter components should be referred to ground. the output of the loop filter is connected to the input voltage pin of the external vco . the output of the vco is brought back into the device on the lop and lon pins , using a balun if necessary . r28 0? (0402) rfin mux r set cp vtune lodrv_en lon lop 2:1 mux vco core temp sensor decl2p5 decl3p3 declvco buffer buffer ifn ifp 2 1 4 5 3 ip3set rf in ? + charge pump 250a, 500a (default), 750a, 1000a prescaler 2 muxout ref_in ADRF6603 19 5 8 36 11 7 4 20 15 23 21 25 24 30 38 35 31 26 phase frequency detector third-order fractional interpolator fraction reg modulus integer reg n counter 21 to 123 2 2 4 divider 2 spi interface c43 10f (0603) c14 22pf (0603) cp test point (orange) c13 6.8pf (0603) c40 22pf (0603) c7 0.1f (0402) vcc red +5v vcc vtune c15 2.7nf (1206) c2 open (0402) c1 100pf (0402) r1 0? (0402) r38 0? (0402) r37 0? (0402) r2 open (0402) c42 10 f (0603) c17 0.1 f (0402) r63 open (0402) r65 10k? (0402) r9 10 k? (0402) r12 0? (0402) r10 3k? (0603) r62 0? (0402) r11 open (0402) rfout c16 100p f (0402) r18 0? (0402) c41 open (0603) c11 0.1 f (0402) c27 0.1 f (0402) c29 0.1 f (0402) c12 100p f (0402) r8 0? (0402) r16 0? (0402) c31 1nf (0402) c6 1nf (0402) r55 open (0402) vcc1 red s1 open r56 0? (0402) c5 1nf (0402) r70 49.9? (0402) 4 lo in/out ref_in refout 3 5 1 t8 tc1-1-13+ r20 0? (0402) r54 10k ? (0402) r19 0? (0402) s2 r53 10k ? (0402) r35 0? (0402) r30 0? (0402) r50 open (0402) r57 0? (0402) r36 0? (0402) p1 9-pin dsub vcc_lo vcc2 vcc1 pll_en clk data le 27 13 12 c8 100pf (0402) r6 0? (0402) c25 0.1f (0402) c24 100pf (0402) r26 0? (0402) c23 0.1f (0402) c22 100pf (0402) r25 0? (0402) c20 0.1f (0402) c21 100pf (0402) r24 0? (0402) c19 0.1f (0402) c18 100pf (0402) r17 0? (0402) c9 0.1f (0402) c10 100pf (0402) r7 0? (0402) 2 4 6 1 3 5 7 c32 open (0402) r51 open (0402) c33 open (0402) r52 open (0402) c34 open (0402) 14 div by 2, 1 vcc_mix vcc_v2i vcc_lo r27 0? (0402) r43 0? (0402) vcc +5v r59 0? (0402) 08547-024 16 2 9 29 18 40 39 3 6 38 37 34 22 17 10 1 8 9 figure 46 . basic connections for operation of the adrf 6603 data sheet ADRF6603 rev. b | page 23 of 32 ac test fixture characterization data for the adrf 6603 was taken under very strict test conditions. all possible techniques we re used to achieve optimum a ccuracy and to remove degradin g effects of the signal generation and measurement equipment. figure 47 shows the typical ac test set up used in the characterization of the adrf 6603. rohde & schwartz fsea30 if_out agilent 34401a set to idc (set for supply current) rf1 agilent n5181a rf2 agilent n5181a ref_in agilent n5181a hp 11636a power divider agilent 34980a with three 34921 modules and one 34950 module ADRF6603 characterization rack diagram. all instruments are controlled by a lab computer via a usb to gpib controller, daisy chained to each individual instrument. ref_in rf in 5v dc via 10-pin dc header 5v dc measured for supply current agilent e3631a 25v set to 3.3v, 6v set to 5v. returns are jumpered together ADRF6603 evaluation board gnd via 10-pin dc header 3.3v dc via 10-pin dc header 9-pin controller dsub and 10-pin dc header 08547-047 figure 47 . adrf 6603 ac test setu p ADRF6603 data sheet rev. b | page 24 of 32 evaluation board figure 50 shows the schematic of the r o hs - compliant evalu a tion board for the adrf 6603 . this board has four layers and was designed using ro gers 4350 hybrid m aterial to minimize high frequency losses. fr4 material is also adequate if the design can accept the slightly hig her trace loss of this material. the evaluation board is designed to operate using the internal vco of the device ( the default configuration) or with an external vco. to use an external vco, r62 and r12 should be removed. place 0 ? resistors in r63 and r11 . the input of the external vco should be connected to the vtune sma connector , and the external vco output should be connected to the lo in/out sma connector. in addition to these hardware changes, internal register settings must also be changed to enable operation with an external vco (see the register 6 vco control and vco enable (default: 0 x 1e2106) section) . additional configuration options for the evaluation board are described in table 10. evaluation b oard control s oftware software to program the adrf 6603 is available for download on the adrf 6603 product page under the evaluation boards & development kits section . to install the software 1. d ownload and extract the zip file : adrf6x0x_ 3 p0p0 _ xp_ install.exe file . 2. follow the instructions in the read me file. the eva luation board can be connected to the pc using a pc parallel port or a usb port. these options are selectable from the opening menu of the software interface (see figure 48 ). the evaluation board is shipped with a 25- pin parallel port cable for connection to the pc parallel port. to connect the evaluation board to a usb port , a usb adapter board ( e va l - adf4xxxz - usb ) must be p urchased from analog devi ces . this board connects to the pc using a standard usb cable with a usb mini - connector at one end. an additional 25 - pin male to 9 - pin female adapter is required to mate the adf4xxxz - usb board to the 9 - pin d - s ub connector on the adrf 6603 evaluation board. 08547-048 figure 48 . control software opening menu figure 49 shows the main menu of the control software with the default settings d isplayed. data sheet ADRF6603 rev. b | page 25 of 32 08547-049 figure 49 . main screen of the adrf 6603 evaluation board software ADRF6603 data sheet rev. b | page 26 of 32 schematic and artwor k 08547-050 agnd agnd agnd agnd agnd nc agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd e-pad vcc cpout gndcp rset refgnd vcc gnddig data clk le gnddig outputen gndbb gndrf vccbb rfrtn nc gndrf vccrf gndrf gndrf inbb ipbb gndbb gnd loexten lon refin vcc_lo vcc_lo vco_ldo 3p3_ldo 2p5_ldo lop vco_in rfin ip3set ifp ifn refout/lock agnd agnd agnd agnd agnd agnd agnd 1 vcc 1 vcc2 1 vcc5 1 vcc_lo1 1 vcc_bb1 1 vcc_rf 1 vcc1 1 vcc_lo 1 vcc4 1 vco_ldo 1 cp 1 data 1 ip3set 1 le 1 clk 1 2p5v 1 osc_3p3v 1 3p3v1 r10 3k r63 100k r37 0 dni r11 r12 0 0 r62 10k r65 r9 10k 22pf c40 c14 22pf c13 6.8pf c15 2.7nf l2 tbd l1 tbd c36 dni c35 dni 0 r66 r67 0 r68 0 dni c41 10uf 0.1uf c9 10uf c42 10uf c43 p1-6 p1-1 1 2 3 4 5 6 7 8 9 p1 amp745781-4 tbd r27 ip3set c34 100pf dni 100pf dni c33 c32 100pf dni 1k dni r52 r51 1k dni 1k dni r50 c28 10uf r47 0 0 r48 vcc vcc 1 2 3 4 5 6 7 8 9 10 11 12 15 16 18 20 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 21 13 14 17 19 pad z1 vcc_bb r60 tbd r44 dni vcc 4 6 1 3 2 t3 tc4-1w r59 0 0 r43 0.1uf c29 c25 0.1uf dni r58 1 dig_gnd r36 0 0 r57 1 2 3 s2 r53 10k 10k r54 r56 10k vcc c31 1000pf r49 dni 1nf c6 c5 1nf lo_extern 0 r33 10k r55 vcc 3 2 1 s1 output_en 0 r30 r19 0 100pf c10 r18 0 dni r2 c12 100pf 0 r25 r26 0 0 r38 r8 0 0 r35 1 gnd 0 r29 vcc 1 j1 y1 r1 0 vcc_sense sns1 sns vco_ldo lo_extern 2p5v_ldo 3p3v_ldo agnd vcc_sense agnd vcc 10 j1 8 j1 r20 0 vcc_bb vcc_lo vcc_rf vcc_bb vcc_lo vcc_lo 0 r28 r14 dni r15 0 c3 10pf c4 22000pf 0.1uf c7 0 r6 c2 0.1uf c1 100pf 100pf c8 0 r7 c11 0.1uf refin refout r16 0 0.1uf c19 100pf c18 c17 0.1uf c16 100pf 0 r17 out c21 100pf r24 0 c20 0.1uf 0.1uf c23 100pf c22 c24 100pf 0.1uf c27 rfin vcc 0 r31 r32 0 0 r34 2 j1 3 j1 4 j1 5 j1 6 j1 7 j1 9 j1 1 gnd1 1 gnd2 vcc_rf ifn ifp osc_3p3v vcc p4-t7 p4-t7 p3-t7 p3-t7 p1-t7 p1-t7 p1-t7 lo 0 r69 1 1a 2 2a 3 3a 4 4a 5 5a 6 6a t7 1 5 3 4 2 t8 p3-t7 p4-t7 output_en ip3set r70 49.9 3p3v_ldo vco_ldo 2p5v_ldo vtune p1-6 r72 0 p1-1 r71 tbd figure 50 . evaluation board schemati c data sheet ADRF6603 rev. b | page 27 of 32 08547-013 figure 51 . evaluation board layout (bottom) 08547-012 figure 52 . evaluation board layout (top) ADRF6603 data sheet rev. b | page 28 of 32 evaluation board c onfiguration options table 10. component description default co ndition/ option settings s1, r55, r56, r33 lo select. switch and resistors to ground the lodrv_en pin. the lodrv_en pin setting , in combination with internal register settings, determines whether the lo p and lon pins function as inputs or outputs (see the lo selection logic section for more information) . s1 = r55 = open (not installed) , r56 = r33 = 0 ? , lodrv_en = 0 v lo in/out sma connector lo input/o utput . an external 1 lo or 2 lo can be applied to this single - ended input connector . lo input refin sma connector reference i nput . the input reference frequency for the pll is applied to this conn ector. input impedance is 5 0 ?. refout sma connector multiplexer output. the refout connector connects directly to the muxout pin. the on- board multiplexer can be programmed to b ring out the following signals: refin, 2 refin, refin/2, and refin/4 ; t em perature sensor o utput v oltage ; and l ock d etect indicator . lock detect cp test point charge p ump t est p oint . the unfiltered charge pump signal can be probed at this test point. note that th e cp pin should not be probed during critical measurements such as phase noise. r37, c14, r9, r10, c15, c13, r65, c40 loop filter . loop filter components . r11, r12 loop f ilter r eturn . when the internal vco is used, the loop filter co mponents should be returned to p in 40 (decl vco ) by installing a 0 ? resistor in r12. when an external vco is used, the loop filter components can be returned to ground by installing a 0 ? resistor in r11 . r12 = 0 ? (0402) , r11 = open (0402) r62, r63, vtune sma connector internal vs. e xternal vco . when the internal vco is enabled, the loop filter components are connect ed directly to the vtune pin (pin 39) by installing a 0 ? resistor in r62. to use an external vco, r62 should be left open. a 0 ? resistor should be installed in r63 , and the voltage input of the vco shoul d be connected to the vtune sma connector. the output of the vco is brought back into the pll via the lo in/out sma connector. r62 = 0 ? (0402) , r63 = open (0402) r2 r set p in . this pin is unused and should be left open . r2 = open (0402) rfin sma connecto r rf i nput . the rf i nput signal should be applied to the rfin sma connector. the rf input of the adrf 6603 is ac - coupled, so no bias is necessary. r3 = r23 = open (0402) t3 if o utput . the dif ferential if o utput s ignal s from the adrf 6603 (ifp and ifn) are converted to a single - ended signal by t3. data sheet ADRF6603 rev. b | page 29 of 32 outline dimensions 1 40 10 1 1 31 30 21 20 compliant t o jedec s t andards mo-220-vjjd-2 06-01-2012-d 0.50 bsc pin 1 indic a t or 4.50 ref 0.20 min 0.50 0.40 0.30 t o p view 12 max 0.80 max 0.65 ty p sea ting plane coplanarit y 0.08 1.00 0.85 0.80 0.30 0.23 0.18 0.05 max 0.02 nom 0.20 ref 4.25 4.10 sq 3.95 0.60 max 0.60 max pin 1 indic a t or 6.10 6.00 sq 5.90 5.85 5.75 sq 5.65 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. exposed pad (bottom view) figure 53 . 40- l ead l ead frame chip scale package [lfcsp_vq] 6 mm 6 mm body, very thin quad ( cp - 40 - 1 ) dimensions shown in millimeters ordering guide model 1 temperature range package description package option adrf 6603 acpz -r7 ? 40c to +85 c 40- lead lead frame chip scale package [lfcsp_vq] cp -40-1 adrf 6603- evalz evaluation board 1 z = rohs compliant part. ADRF6603 data sheet rev. b | page 30 of 32 notes data sheet ADRF6603 rev. b | page 31 of 32 notes ADRF6603 data sheet rev. b | page 32 of 32 notes ? 2010 C 2013 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d08547 - 0 - 10/13(b) |
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